The present invention relates to a voltage generation circuit, and more particularly, to an internal voltage generation circuit that generates an internal voltage used for a semiconductor memory device.
In general, a semiconductor memory device generates various internal voltages each having a uniform level for a stable operation. In particular, a semiconductor memory device generates and provides a back bias voltage to its MOS transistors in order to reduce leakage currents and to stabilize the threshold voltage.
The internal voltages including the back bias voltage must be maintained to a voltage level in a predetermined range regardless of any changes in processes, voltage, and temperature (PVT) for a stable operation. Therefore, a detection circuit for detecting a change in the internal voltage level must be provided in order to maintain an internal voltage level in a uniform range.
A conventional back bias voltage detection circuit as shown in FIG. 1 outputs a detection signal DET0 based on the turn on resistance difference of PMOS transistors P1 and P2 by monitoring the internal power source voltage VINT, the external ground voltage VSS, and the back bias voltage VBB, as their voltage levels change internally.
That is, when the level of the back bias voltage VBB becomes lower than the level of the ground voltage VSS, the voltage formed between the gate and the source of the PMOS transistor P2 will increase, which will in turn cause the resistance of the PMOS transistor P2 to be lower than the resistance of the PMOS transistor P1. Then, the potential at the node ND1 would vary in response to the changes in the resistance ratio between the PMOS transistors P1 and P2.
When the potential at the node ND1 is less than the threshold voltage of an MOS transistor-type pull-up device having an inverter INV, the detection signal DET0 would transition from the ground voltage VSS to the power source voltage VDD by the MOS transistor-type pull-up device.
The transition point of the detection signal DET0 can be set to a predetermined level previously by controlling the sizes of the PMOS transistors P1 and P2. The level of the back bias voltage VBB is controlled in response to the transition point of the detection signal DET.
That is, the conventional back bias voltage detection circuit as shown in FIG. 1 monitors the changes in the back bias voltage VBB level through the operations of the PMOS transistors P1 and P2 and the inverter INV to output the detection signal DET0, and the level of the back bias voltage VBB is controlled in accordance with the state of the detection signal DET0.
However, problems lie in that the level of the internal power source voltage VINT or the characteristics of the PMOS transistors P1 and P2 and the inverter INV can change as the process conditions change in the conventional back bias voltage detection circuit shown in FIG. 1.
In this case, now referring to FIG. 2, the voltage level variations at the node ND1 become severe causing the detection signal DET0 level to vary widely such that the skew of the detection point becomes large.